Deadlock-free verification and performance enhancement of RosettaNet PIPs with time Petri nets
Liao, Da-Yin, Liu, PaladinVolume:
18
Language:
english
Journal:
International Journal of Computer Integrated Manufacturing
DOI:
10.1080/0951192052000288170
Date:
March, 2005
File:
PDF, 297 KB
english, 2005