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[IEEE 2014 IEEE Symposium on VLSI Technology - Honolulu, HI, USA (2014.6.9-2014.6.12)] 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers - Design methodology of tri-gate poly-Si MOSFETs with 10nm nanowire channel to enhance short-channel performance and reduce Vth & Id variability
Saitoh, Masumi, Ota, Kensuke, Tanaka, Chika, Numata, ToshinoriYear:
2014
Language:
english
DOI:
10.1109/vlsit.2014.6894425
File:
PDF, 432 KB
english, 2014