A 26–28-Gb/s Full-Rate Clock and Data Recovery...

IEEE Transactions on Circuits and Systems I: Regular Papers 2014 / 7 Vol. 61; Iss. 7

A 26–28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS

Sun, Li, Pan, Quan, Wang, Keh-Chung, Yue, C. Patrick
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Volume:
61
Language:
english
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
DOI:
10.1109/tcsi.2014.2304669
Date:
July, 2014
File:
PDF, 2.97 MB
english, 2014
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