Hardware Architecture for List Successive Cancellation...

IEEE Transactions on Circuits and Systems II: Express Briefs 2014 / 8 Vol. 61; Iss. 8

Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

Balatsoukas-Stimming, Alexios, Raymond, Alexandre J., Gross, Warren J., Burg, Andreas
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Volume:
61
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/tcsii.2014.2327336
Date:
August, 2014
File:
PDF, 979 KB
english, 2014
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