Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits:...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2014 / 12 Vol. 22; Iss. 12

Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives

Alioto, Massimo, Esseni, David
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Volume:
22
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2013.2293153
Date:
December, 2014
File:
PDF, 4.48 MB
english, 2014
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