A systolic architecture for modulo multiplication

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 1995 / Nov. Vol. 42; Iss. 11

A systolic architecture for modulo multiplication

Elleithy, K.M., Bayoumi, M.A.
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Volume:
42
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
DOI:
10.1109/82.475251
Date:
January, 1995
File:
PDF, 433 KB
english, 1995
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