Zero-aware asymmetric SRAM cell for reducing cache power in...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2004 / 08 Vol. 12; Iss. 8

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero

Yen-Jen Chang,, Feipei Lai,, Chia-Lin Yang,
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Volume:
12
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2004.831471
Date:
August, 2004
File:
PDF, 942 KB
english, 2004
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