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[IEEE 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Liberec, Czech Republic (2009.04.15-2009.04.17)] 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories
Borowik, Grzegorz, Luba, Tadeusz, Falkowski, Bogdan J.Year:
2009
Language:
english
DOI:
10.1109/DDECS.2009.5012135
File:
PDF, 272 KB
english, 2009