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[IEEE 2007 IEEE International Interconnect Technology Conferencee - Burlingame, CA, USA (2007.06.4-2007.06.6)] 2007 IEEE International Interconnect Technology Conferencee - BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability
Kwak, Nohjung, Ahn, Sang-Tae, Park, Hyung-Soon, Kim, Seo-Min, Jung, Jin-Ki, Kim, Gyu-Hyun, Choi, Geun-Young, Koo, Dong-Chul, Jung, Tae-Oh, Ku, Ja-Chun, Jung, Jae-Kwan, Kim, Jinwoong, Park, Sungwook, SYear:
2007
Language:
english
DOI:
10.1109/iitc.2007.382367
File:
PDF, 486 KB
english, 2007