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[IEEE 2007 IEEE Symposium on VLSI Technology - Kyoto, Japan (2007.06.12-2007.06.14)] 2007 IEEE Symposium on VLSI Technology - A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node
Tsutsui, Gen, Maruyama, Shinya, Abe, Tomohisa, Nakamura, Hidetatsu, Fukase, TadashiYear:
2007
Language:
english
DOI:
10.1109/vlsit.2007.4339682
File:
PDF, 637 KB
english, 2007