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[IEEE Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. - Honolulu, HI, USA (2004.06.17-2004.06.17)] Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004. - Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode
Togo, M., Fukai, T., Nakahara, Y., Koyama, S., Makabe, M., Hasegawa, E., Nagase, M., Matsuda, T., Sakamoto, K., Fujiwara, S., Goto, Y., Yamamoto, T., Mogami, T., Ikeda, M., Yamagata, Y., Imai, K.Year:
2004
Language:
english
DOI:
10.1109/vlsit.2004.1345409
File:
PDF, 195 KB
english, 2004