[IEEE 2007 IEEE Symposium on VLSI Technology - Kyoto, Japan (2007.06.12-2007.06.14)] 2007 IEEE Symposium on VLSI Technology - Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner
Zhu, Huilong, Yang, Daewon, Kumar, Mahender, Colt, John, Maxson, Jeff, Scholl, Fred, Chen, Derek, Leach, Deb, Leobandung, EffendiYear:
2007
Language:
english
DOI:
10.1109/vlsit.2007.4339684
File:
PDF, 789 KB
english, 2007