[IEEE 2008 Symposium on VLSI Technology - Honolulu, HI, USA (2008.06.17-2008.06.19)] 2008 Symposium on VLSI Technology - Performance enhancement schemes featuring lattice mismatched S/D stressors concurrently realized on CMOS platform: e-SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant

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