![](/img/cover-not-exists.png)
[IEEE 2010 15th Asia and South Pacific Design Automation Conference ASP-DAC 2010 - Taipei, Taiwan (2010.01.18-2010.01.21)] 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) - Minimizing clock latency range in robust clock tree synthesis
Wen-Hao L,, Yih-Lang Li,, Hui-Chi Chen,Year:
2010
Language:
english
DOI:
10.1109/aspdac.2010.5419849
File:
PDF, 292 KB
english, 2010