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[Widerkehr and Associates 2004 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (17-19 June 2004)] 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) - A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme
Young-Soo Sohn,, Jung-Hwan Choi,, In-Young Chung,, HoeJu Chung,, Chan-Kyoung Kim,, Gyoung-Su Byun,, Dae-Woon Kang,, Won-Ki Park,, In-Soo Park,, Hong-Sun Hwang,, Chang-Hyun Kim,, Soo-In Cho,Year:
2004
Language:
english
DOI:
10.1109/vlsic.2004.1346493
File:
PDF, 163 KB
english, 2004