[IEEE 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2008.04.23-2008.04.25)] 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS
Hsiang-Hui Chang,, Shang-Ming Lee,, Chao-Wen Chou,, Yu-Tung Chang,, Yi-Li Cheng,Year:
2008
Language:
english
DOI:
10.1109/vdat.2008.4542400
File:
PDF, 1.11 MB
english, 2008