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[IEEE 2008 Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) - Seoul, Korea (South) (2008.12.10-2008.12.12)] 2008 Electrical Design of Advanced Packaging and Systems Symposium - Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory
Hao-Hsiang Chuang,, Shu-Jung Wu,, Ming-Zhang Hong,, Hsu, Darren, Huang, Raphael, Li Chang Hsiao,, Tzong-Lin Wu,Year:
2008
Language:
english
DOI:
10.1109/edaps.2008.4735991
File:
PDF, 1.18 MB
english, 2008