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[Japan Soc. Appl. Phys 2003 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (12-14 June 2003)] 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) - 10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 μm digital CMOS process
Ravi, A., Banerjee, G., Bishop, R.E., Bloechel, B.A., Carley, L.R., Soumyanath, K.Year:
2003
Language:
english
DOI:
10.1109/vlsic.2003.1221197
File:
PDF, 340 KB
english, 2003