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[IEEE Technology of Integrated Systems in Nanoscal Era (DTIS) - Cairo, Egypt (2009.04.6-2009.04.9)] 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era - Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing
Shinogi, Tsuyoshi, Arakawa, Kanako, Hayashi, TerumineYear:
2009
Language:
english
DOI:
10.1109/dtis.2009.4938061
File:
PDF, 942 KB
english, 2009