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[IEEE IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06) - KLarlsruhe, Germany (02-03 March 2006)] IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06) - Verification of Scheduling in High-level Synthesis
Karfa, C., Mandal, C., Sarkar, D., Pentakota, S.R., Reade, C.Volume:
00
Year:
2006
Language:
english
DOI:
10.1109/isvlsi.2006.93
File:
PDF, 213 KB
english, 2006