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[IEEE Comput. Soc 5th International Symposium on Quality Electronic Design - San Jose, CA, USA (22-24 March 2004)] SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720) - Cost model analysis of DFT based fault tolerant SOC designs
Sundararaman, K., Upadhyaya, S., Margala, M.Year:
2004
Language:
english
DOI:
10.1109/isqed.2004.1283717
File:
PDF, 290 KB
english, 2004