[IEEE 2008 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2008.06.18-2008.06.20)] 2008 IEEE Symposium on VLSI Circuits - A fully logic-process-compatible, 3-transistor, SESO-memory cell featuring 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention
Kameshiro, N., Watanabe, T., Ishii, T., Mine, T., Sano, T., Ibe, H., Akiyama, S., Yanagisawa, K., Ipposhi, T., Iwamatsu, T., Takahashi, Y.Year:
2008
Language:
english
DOI:
10.1109/vlsic.2008.4585976
File:
PDF, 758 KB
english, 2008