![](/img/cover-not-exists.png)
[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations
Zhang, Fengming, Necoechea, Warren, Reiter, Peter, Kim, Yong-bin, Lombardi, FabrizioYear:
2006
Language:
english
DOI:
10.1109/dft.2006.38
File:
PDF, 225 KB
english, 2006