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An AES crypto chip using a high-speed parallel pipelined architecture
S.-M. Yoo, D. Kotturi, D.W. Pan, J. BlizzardVolume:
29
Year:
2005
Language:
english
Pages:
10
DOI:
10.1016/j.micpro.2004.12.001
File:
PDF, 533 KB
english, 2005