Designing for reliability using a new Wafer Level Package...

Microelectronics Reliability 2010 Vol. 50; Iss. 4

Designing for reliability using a new Wafer Level Package structure

P.H. Hochstenbach, W.D. van Driel, D.G. Yang, J.J.M. Zaal, E. Bagerman
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Volume:
50
Year:
2010
Language:
english
Pages:
8
DOI:
10.1016/j.microrel.2009.09.011
File:
PDF, 1.32 MB
english, 2010
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