Reliability of VLSI-level chip assembly for evaluating the...

IEEE Transactions on Device and Materials Reliability 2002 / 09 Vol. 2; Iss. 3

Reliability of VLSI-level chip assembly for evaluating the development of back-end technologies using a test chip with a top two-level metal structure

Kuo-Yu Chou,, Ming-Jer Chen,, Chi-Wen Liu,, Bing-Hong Lin,
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Volume:
2
Language:
english
Journal:
IEEE Transactions on Device and Materials Reliability
DOI:
10.1109/tdmr.2002.804397
Date:
September, 2002
File:
PDF, 1.01 MB
english, 2002
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