[IEEE 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Warsaw, Poland (2014.4.23-2014.4.25)] 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Design methodology of configurable high performance packet parser for FPGA
Pus, Viktor, Kekely, Lukas, Korenek, JanYear:
2014
Language:
english
DOI:
10.1109/ddecs.2014.6868788
File:
PDF, 562 KB
english, 2014