[IEEE 22nd IEEE VLSI Test Symposium, 2004. - Napa Valley, CA, USA (25-29 April 2004)] 22nd IEEE VLSI Test Symposium, 2004. Proceedings. - Logic BIST using constrained scan cells
Liyang Lai,, Rinderknecht, T., Wu-Tung Cheng,, Patel, J.H.Year:
2004
Language:
english
DOI:
10.1109/vtest.2004.1299244
File:
PDF, 1.47 MB
english, 2004