Temperature scaling for 35 nm gate length...

Materials Science in Semiconductor Processing 2004 Vol. 7; Iss. 4-6

Temperature scaling for 35 nm gate length high-performance CMOS

Th. Feudel, M. Horstmann, M. Gerhardt, M. Herden, L. Herrmann, D. Gehre, Ch. Krueger, D. Greenlaw, M. Raab
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Volume:
7
Year:
2004
Language:
english
Pages:
6
DOI:
10.1016/j.mssp.2004.09.063
File:
PDF, 579 KB
english, 2004
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