Design and optimization of two-bit double-gate nonvolatile...

IEEE Transactions on Nanotechnology 2006 / 05 Vol. 5; Iss. 3

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

Seongjae Cho,, Il Han Park,, Tae Hun Kim,, Jae Sung Sim,, Ki-Whan Song,, Jong Duk Lee,, Hyungcheol Shin,, Byung-Gook Park,
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Volume:
5
Language:
english
Journal:
IEEE Transactions On Nanotechnology
DOI:
10.1109/tnano.2006.869943
Date:
May, 2006
File:
PDF, 601 KB
english, 2006
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