IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2013 / 7 Vol. 32; Iss. 7
Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs
Chiao-Ling Lung,, Yu-Shih Su,, Hsih-Hsiu Huang,, Yiyu Shi,, Shih-Chieh Chang,Volume:
32
Language:
english
Journal:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI:
10.1109/tcad.2013.2245375
Date:
July, 2013
File:
PDF, 904 KB
english, 2013