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[IEEE 2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs - Richardson, TX, USA (10-10 Oct. 2005)] 2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs - Yield Aware Design Methodology for Sub-100-Nanometer Digital SOC Designs
Sundaram, C., Balsara, P.T., Vemulapalli, S.K., Vallur, P.K., Eliezer, O.E.Year:
2005
Language:
english
DOI:
10.1109/dcas.2005.1611178
File:
PDF, 732 KB
english, 2005