Efficient logic-level timing analysis using...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1996 / 09 Vol. 4; Iss. 3

Efficient logic-level timing analysis using constraint-guided critical path search

Chanhee Oh,, Mercer, M.R.
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Volume:
4
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/92.532035
Date:
September, 1996
File:
PDF, 1.09 MB
english, 1996
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