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[IEEE 2008 15th International Symposium on Temporal Representation and Reasoning (TIME) - Montreal, Quebec, Canada (2008.06.16-2008.06.18)] 2008 15th International Symposium on Temporal Representation and Reasoning - Efficient Bit-Level Model Reductions for Automated Hardware Verification
Tverdyshev, Sergey, Alkassar, EyadYear:
2008
Language:
english
DOI:
10.1109/time.2008.11
File:
PDF, 394 KB
english, 2008