Multiple Threshold Voltage Design Scheme for CMOS Tapered...

IEEE Transactions on Circuits and Systems II: Express Briefs 2008 / 01 Vol. 55; Iss. 1

Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers

Shebaita, Ahmed, Ismail, Yehea
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
55
Language:
english
Journal:
IEEE Transactions on Circuits and Systems II: Express Briefs
DOI:
10.1109/tcsii.2007.907784
Date:
January, 2008
File:
PDF, 947 KB
english, 2008
Conversion to is in progress
Conversion to is failed