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[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - 1-Gb/s/pin multi-gigabit DRAM design with low impedance hierarchical I/O architecture
Fujisawa, H., Takahashi, T., Yoko, H., Fujii, I., Takai, Y., Nakamura, M.Year:
2002
Language:
english
DOI:
10.1109/vlsic.2002.1015061
File:
PDF, 170 KB
english, 2002