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[IEEE 2014 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2014.4.28-2014.4.30)] Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test - Low power pipelined SAR ADC with loading-free architecture
Wu, Jia-Jhang, Chang, Soon-Jyh, Lin, Sheng-Hsiung, Huang, Chun-Po, Huang, Guan-YingYear:
2014
Language:
english
DOI:
10.1109/vlsi-dat.2014.6834906
File:
PDF, 1.00 MB
english, 2014