[IEEE Design, Automation and Test in Europe - Munich, Germany (07-11 March 2005)] Design, Automation and Test in Europe - Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
Beck, M., Barondeau, O., Kaibel, M., Poehl, F., Xijiang Lin,, Press, R.Year:
2005
Language:
english
DOI:
10.1109/date.2005.199
File:
PDF, 198 KB
english, 2005