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[IEEE 2010 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2010) - Bologna, Italy (2010.09.6-2010.09.8)] 2010 International Conference on Simulation of Semiconductor Processes and Devices - Compact process and layout aware model for variability optimization of circuit in nanoscale CMOS
Kim, Yo-Han, Jeon, Jong-Wook, Jang, Yong-Un, Park, Yong-Hee, Yang, Gi-Young, Park, Young-Kwan, Yoo, Moon-Hyun, Chung, Chil-HeeYear:
2010
Language:
english
DOI:
10.1109/sispad.2010.5604545
File:
PDF, 1.63 MB
english, 2010