[IEEE 2007 IEEE Symposium on VLSI Circuits - Kyoto, Japan (2007.06.14-2007.06.16)] 2007 IEEE Symposium on VLSI Circuits - A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H., Akamatsu, H.Year:
2007
Language:
english
DOI:
10.1109/vlsic.2007.4342740
File:
PDF, 2.54 MB
english, 2007