Elimination of poly-Si gate depletion for sub-65-nm CMOS...

IEEE Electron Device Letters 2005 / 04 Vol. 26; Iss. 4

Elimination of poly-Si gate depletion for sub-65-nm CMOS technologies by excimer laser annealing

Hiu Yung Wong,, Takeuchi, H., Tsu-Jae King,, Ameen, M., Agarwal, A.
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Volume:
26
Language:
english
Journal:
IEEE Electron Device Letters
DOI:
10.1109/led.2005.845502
Date:
April, 2005
File:
PDF, 217 KB
english, 2005
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