Latch Design Techniques for Mitigating Single Event Upsets...

Latch Design Techniques for Mitigating Single Event Upsets in 65 nm SOI Device Technology

KleinOsowski, AJ, Cannon, Ethan H., Gordon, Michael S., Heidel, David F., Oldiges, Phil, Plettner, Cristina, Rodbell, Kenneth P., Rose, Ronald D., Tang, Henry H. K.
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Volume:
54
Language:
english
Journal:
IEEE Transactions on Nuclear Science
DOI:
10.1109/tns.2007.909707
Date:
December, 2007
File:
PDF, 238 KB
english, 2007
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