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[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs
Bahukudumbi, Sudarshan, Chakrabarty, KrishnenduYear:
2007
Language:
english
DOI:
10.1109/vlsid.2007.157
File:
PDF, 448 KB
english, 2007