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[IEEE 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu, Taiwan (2008.04.23-2008.04.25)] 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Synthesis of a timing-error detection architecture
Yu-Shih Su,, Po-Hsien Chang,, Shih-Chieh Chang,, TingTing Hwang,Year:
2008
Language:
english
DOI:
10.1109/vdat.2008.4542437
File:
PDF, 328 KB
english, 2008