[IEEE 2013 IEEE International Electron Devices Meeting (IEDM) - Washington, DC, USA (2013.12.9-2013.12.11)] 2013 IEEE International Electron Devices Meeting - Comprehensive layout and process optimization study of Si and III-V technology for sub-7nm node
Kang, C. Y., Baek, R-H., Kim, T-W, Ko, D., Kim, D-H., Michalak, T., Borst, C., Veksler, D., Bersuker, G., Hill, R., Hobbs, C., Kirsch, P. D.Year:
2013
Language:
english
DOI:
10.1109/iedm.2013.6724566
File:
PDF, 1.92 MB
english, 2013