Modeling a verification test system for mixed-signal...

IEEE Design & Test of Computers 2001 / Jan.-Feb. Vol. 18; Iss. 1

Modeling a verification test system for mixed-signal circuits

Bello, D.S.S., Tangelder, R., Kerkhoff, H.
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Volume:
18
Language:
english
Journal:
IEEE Design & Test of Computers
DOI:
10.1109/54.902823
Date:
January, 2001
File:
PDF, 590 KB
english, 2001
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