An integrated reset/pulse pile-up rejection circuit for...

IEEE Transactions on Nuclear Science 2006 / 02 Vol. 53; Iss. 1

An integrated reset/pulse pile-up rejection circuit for pixel readout ASICs

Bastia, P., Bertuccio, G., Borghetti, F., Caccia, S., Ferragina, V., Ferrari, F., Maiocchi, D., Malcovati, P., Martin, D., Pullia, A., Ratti, N.
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Volume:
53
Language:
english
Journal:
IEEE Transactions on Nuclear Science
DOI:
10.1109/tns.2006.869852
Date:
February, 2006
File:
PDF, 652 KB
english, 2006
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