Understanding yield losses in logic circuits
Appello, D., Fudoli, A., Giarda, K., Tancorre, V., Gizdarski, E., Mathew, B.Volume:
21
Language:
english
Journal:
IEEE Design and Test of Computers
DOI:
10.1109/mdt.2004.21
Date:
May, 2004
File:
PDF, 368 KB
english, 2004