Architectural implications and process development of 3-D...

IEEE Transactions on Advanced Packaging 2005 / 08 Vol. 28; Iss. 3

Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias

Schaper, L.W., Burkett, S.L., Spiesshoefer, S., Vangara, G.V., Rahman, Z., Polamreddy, S.
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Volume:
28
Language:
english
Journal:
IEEE Transactions on Advanced Packaging
DOI:
10.1109/tadvp.2005.853271
Date:
August, 2005
File:
PDF, 2.79 MB
english, 2005
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