Design-for-Test Techniques for Opens in Undetected Branches...

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2007 / 05 Vol. 15; Iss. 5

Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops

Zenteno Ramirez, Antonio, Espinosa, Guillermo, Champac, Victor
How much do you like this book?
What’s the quality of the file?
Download the book for quality assessment
What’s the quality of the downloaded files?
Volume:
15
Language:
english
Journal:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI:
10.1109/tvlsi.2007.896910
Date:
May, 2007
File:
PDF, 684 KB
english, 2007
Conversion to is in progress
Conversion to is failed